Semiconductor modules, such as semiconductor chips provided with a package, which for electrically connecting, for example, with a circuit board, are provided with connections, which are, for example, provided in the form of solder bumps, should be very reliable. Thus, the semiconductor modules should not only be reliable with regard to their function but also a reliable lasting contacting connection with, for example, a circuit board, should be ensured.
One of the problems with semiconductor modules is the thermo-mechanical adaptation of the integrated circuits and semiconductor chips (mostly silicon), respectively, to the next level, i.e., for example to a printed circuit board (PCB). This problem exists due to the coefficients of thermal expansion (CTEs) of the materials being different from each other. The material of a conventional printed circuit board (PCB), for example, an adaptation to copper, has a CTE of approximately 15 ppm/K to 16 ppm/K, and the CTE of silicon is of approximately 3 ppm/K.
This is the reason why a plurality of different types of packages has been created to reduce the thermo-mechanical stress factor. In some of the package types, a substrate is used as an intermediate element (such as, for example, ball grid array (BGA), flip chip in package), by which it is attempted to balance the thermo-mechanical mismatch within the arrangement to be as low as possible at a certain range of temperature. However, in the case of using packages accommodating bare dies (wafer level package), the situation becomes increasingly critical due to the fact that the chips are arranged in very close contact to the board of the next level.
Consequently, one challenge for the packaging industry is to produce packages for integrated circuits, such as bare dies with a low complexity, which are very reliable, have small dimensions, and can be produced at low costs.
In flip-chip packages (FCiPs), for example, a plurality of functional elements is included to fulfill all package functions and to provide a balance with regard to the thermo-mechanical stress adaptation between chip/substrate and substrate/board. For this purpose, for example, the following are provided: solder balls on the chip (sometimes using a redistribution level); bonding of the chips to the substrate by using underfill; the substrate itself, large ball grid array (BGA) solder balls to realize the electrical and mechanical connection to the next level; and mold compound as backside and edge protection.
In the case of wafer level packages (WLPs) the crossing of critical material parameters (mainly with regard to the CTE) is the greatest challenge: between the chip and the next level often only BGA solder balls are arranged; in the case of a necessary redistribution of the chip pads often a dielectric buffer layer is used; and pillars under the solder balls are known, which increase the distance or gap between the chip and the substrate.
WLPs of a greater size (distance to the neutral point of the balls (DNP) >3 mm to 4 mm) are not reliable enough for most applications due to stress-induced internal cracks.